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Sony DVP-M35 Operation Manual
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Sony DVP-M35 Operation Manual

Sony DVP-M35 Operation Manual

Cd/dvd player
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DVP-M35/S300/S305/S315/
S500D/S 505D/$715
OPERATION
MANUAL
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CD/DVD PLAYER

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Summary of Contents for Sony DVP-M35

  • Page 1 DVP-M35/S300/S305/S315/ S500D/S 505D/$715 OPERATION MANUAL CD/DVD PLAYER...

  • Page 2: Table Of Contents

    Contents 1. Outline ............................ 1-1. Series line-up .......................6 1-2. External appearance diagram ..................7 1-3,.Internal appearance diagram (top view) ..............8 1-4. Disc drive unit ......................10 1-5. Block diagram ......................2. SIGNAL PROCESSING BLOCK ..............15 2-1. DVD RF FRONT END ..................15 2-1-1.
  • Page 3 3. SERVO BLOCK ......................3-1. General Description of Servo Circuits ............... 33 3-1-1. Optical Pickup Control ..................3-1-2. Sled Control ......................3-1-3. Spindle Control ...................... 3-1-4. Tilt Control ......................3-I-5. Disc Loading and Chucking .................. 3-1-6. Disc Judgment ....................... 3-2. Servo Operation at DVD Play ................34 3-2-1.
  • Page 4 4-5. Large Gate Array CXD8728 (IC804 on MB-78 board) ........ 4-5-1. Block Diagram ....................7..72 4-5-2. Pin Functions ......................4-6. Middle Gate Array CXD8746 (IC 101 on MB-78 board) ......78 4-6-1. Block Diagram ....................... 4-6-2. Pin Functions ......................' 4-7. Small Gate Array CXD8747 (IC807...

  • Page 5: Outline

    Outline This guidebook describes the DVD-Video. It also describes the functions not used in the DVP Series. For the functions used in the DVP Series, refer to Secions 2 to 5, or Service Manual. 1-1. Series line-up Basic Dolby digital model DVP-S500D NTSC U/C specifications (120V)

  • Page 6: External Appearance Diagram

    *Output terminal 21P Euro (DVP-S315, $715) S terminal, video, audio x l Note: Video-CDs recorded in the PAL format can be played only by general overseas specifications models. 1-2. External appearance diagram Basic Dolby digital models DVP-S'500D DVP-S501D/S505D 98ram ± 280 size models 91mm...
  • Page 7 Basic models DVP-S300/S305/S315 ± DVP-S715 1-3. Internal appearance diagram (top view) Basic Dolby digital models YS board (COMPONENT VIDEO) AU board (AUDIO) .__.__F3 ......Power block (SWITCHING REGULATOR HP board (DVP-S300/S315) MB board (HEAD PHONE) (SIGNAL PROCESS/SERVO) ME board (DVP-S305) (MIC) LE board Disc drive unit...
  • Page 8 280 size models POWER BLOCK _.. AU-board MB-board HP board (HEAD PHONE) I o,sco ,vou , FL board --.., FRONT SIDE LE board Basic models PS board (DVP-S715) Power transformer AU board (AUDIO POWER) (DVP-S715) (AUDIO) ER board (DVP-S315/S715) (EURO AV) .....

  • Page 9: Disc Drive Unit

    1-4. Disc drive unit 1) Configuration of disc drive unit. [Optical block specifications] CD system OPT DVD system OPT Tilt motor Skew adjustment i Thread motor Configuration of thread system Spindle motor Tilt sensor Optical block ass'y Specification DVD system DC system Non-deflection, Non-deflection,...
  • Page 10 2) Optical route diagram Objec ator _..lens Mirror _)_._,._ ' ' -_"_ OEIC ForCD Laser diode For DVD -11-...

  • Page 12: Block Diagram

    1-5. Block diagram I.... COAX &(_) 256K SRAM 2CHLP F AC-3 IMB BOARD 1 4M DRAM SDRAM Lc8D910R51v (MBA8C63342)6CH DSP __l]__ 2C_PFB_F ___l--;__ ITKBOARD I AU-L,R © MPEG SPDIF DVDFRONT END ..____.1 _PF---_ "l I 2CH DAC I BUFF I SHSerial I F_ (SSI33P3720)

  • Page 13: Signal Processing Block

    2-1-1. Attenuation of OP Output Signals Signal Processing Block The RF signals (RFP, RFM) output from OP for DVD are attenuated by R066 and R064 so that they satisfy the input amplitude allowable level of IC006 in the post Block which perfornls various signal proccssings from the RF frollt cnd to the output of stage.
  • Page 14 Theinputsignal t o IC006DIP_ andDIN_) is a signal p rocessed afterEQ block mentioned l ater. "1: SingleLayerdisc *2: DualLayerdisc *3: Peak to Peak Differential (3) EQblock TheEQblockis a programmable equalizer filter differentiator block. TheDVD formatis premised o n theEQ andrequires h ighfrequency signals tobe boosted.
  • Page 15 (4) Serial interface Various values of IC006 are set to internal serial port register via serial interface. Actually, they are set by three signals from the L G/A IC804. Signals are SDEN_, SDATA_), and SCLK(_, and its timing chart is shown in Figure 2-5. SDEN SDATA ADDRESS,...

  • Page 16: Cd Rf Front End

    2-2. CD RF Front End rTK-47 board CXA,?.5550 OPTICAL BLOCK CDRF TK-47 board < cNO01 To MB-78 board IC.806 ARP Figure 2-6. TK-47 board RF/CD The RF signal output from the CD OP is input to IC005 (_) and (_), and transmitted to IC806ARP of the MB-78 board via the amplifier, equalizer.

  • Page 17: Rf Signal Processing Block

    2-3. RF Signal Processing Block The block is composed of the IC806 ARP (CXD 1865R) and IC810 4Mbit DRAM (I.tPD424260) of the MB-78 board. In the case of the DVD, the ARP is input with the AGC and RF equalize-processed DVD-RF signal at the IC006 analog front end (SSI33P3720) of the TK-47 board.

  • Page 18: Decrypt Block

    2-4. Decrypt Block Data sent from ARP is subject to decoding of the digital copy protection for preventing illegal copy determined by DVD standards at ICS11 (CXD1904), and then sent to the AV decoder in the post stage. 2-5. AV Decoder Block Comp0sed of two 16M SDRAMs (IC201,202MB 81117622)
  • Page 19 IC203 AV Decoder (L64020) YC0-7 DCRSD 0-7 To IC251 DNR AU-197 0353 ERROR AVALID AREQ iC351 _ C°axial °utptzt ] 0joltal IC207 GPIF32T output MB90096 FromIC807 ('CG--'_'O SGA , _SO CXD08747 ' L SCLKO IC102 OIR (To LC8905t) AVDATA AV LRCK AVBCK To IC101 MGA (2cll signal) FromIC806ARP...

  • Page 20: 2-7,. Dnr, Video Encoder Blocks

    2-7. DNR, Video Encoder Blocks The video data from the AV decoder is sent to IC251, DNR (CXD1854), subjected to video noise reduction, and sent to the IC252 video encoder CXD1914 in the post stage. The video data is converted to NTSC/PAL video signal (Color difference signal/S-Y, S-C/composite) here.

  • Page 21: Clock Generation Block

    2-8. Clock Generator Block The IC209 CXD8696PLL IC generates 27 MHz, and using this as the master clock, generates the system clock for audio decoding. System Clock 384fs 768fs CD/VCD 16.9344 MHz 33.8688 MHz 18.4320 MHz 36.8640 MHz IC209 IC206 SN74ABT12608 CXD8696 BUFF 27.0000MHz...

  • Page 22: Decoder Block

    2-9. AC-3 Decoder Block M G/A (IC101) CXO 87460 FromL_A (tC_4) 8s'r 6STC $062C SCKG2 From _ 11c8o5) ; SOG2 AC-3 AC3__K OR LRCK ( DECODER DO_LRCK AC;_LRCK (IC_04) M886342 DD_BCK AC3_DATA F AC3_OATA R AC3.OATA C DD_OATA F 256KS_ N341256 Figure 2-13.

  • Page 23: Audio L, R 2Ch Signal Block

    2-10. Audio L and R 2ch Signal Block The audio signal data for 2 channels of the MB-78 board AV decoder IC203 (L64020) is passed through IC101MGA, passed through the digital filter in the AU197 board IC215 (CXD8750), converted to analog signal in the DAC, and passed through the LDF to become the line out signal.

  • Page 24: Audio 5. Lch Signal Block

    2-11. Audio 5.1ch Signal Block The AC3 decoded signal DD-DATA C/R/F output from the MB-78 board IC101 (CXD8746) is input together with DD BCK and DD LRCK to IC203, IC204, and IC205 (CXD8750) of the AU-197 board, passed through the digital filter, and converted to the analog signal in DAC.

  • Page 25: Dvp-S715 Au-205 Board Block Diagram

    2-12. DVP-S715 AU-205 Board Block Diagram 1/2 _CL_I7 1/2 IC207 L P, F BUFFER J202 OAC BCK CLOCK BUFFER DA, C LRCK L OUT CN203 AOATA 0211 0203 FILTER MUTE SWITCH R OUT 0212 IC208 HP, L ;" _ ,CN205 Q204 MUTE FILTER...

  • Page 26: System Control Block

    2-13. System Control Block The system controller is composed mainly of the IC805 (HD6437034) SH microcomputer, IC807 (CXD8728) large gate array, 1C802 (HM62812) 1M SRAM, ICS803 8M FLASH memory, and IC807 (CXD8747) small gate array, etc. It serves to control the overall servo system. 2-14.
  • Page 28 1(3803 Vcc=5v IC802 Vcc=5v IC 506 Vcc=5V IC 806 Vcc=3.3V IC 811 Vcc=5V IC 203 Vcc=3.3V ROM(Flash)SMbit Servo DSP DECRIPT AV_DEC RAM (1Mbit) CXD8730 CXD1865 HM628128 CXD 1904 L64020 Ai, d ,'-" I-- _--I._. _ _ _z_ ,,'- Vcc=5V BusBuffer o,1o "__ (SGA) O'3 (:3...

  • Page 29: Servo Block

    SERVO BLOCK 3-2. Servo Operation at DVD Play 3-2-1. Optical Pickup Control 3-1. General Description of Servo Circuits (1) DVD focus servo The focus error signal output from the optical pickup for DVD (hereinafter referred to as optical pickup) is entered to the TK-47 board IC006: SSI33P3720A A to D ((_ to 3-1-1.
  • Page 30 MB-78 board TK-47 board Optical Block IC006 SS133P3720A IC506 IC363 tC452 iC503 (1/4,3/4) CNO01 MC14053 CXD8730R BA5981 NJM3403 CNO05 CN452 FCSDRtVE SERVODSP DVD FCS--_ To DVD FOCUS coil DVDFCS+_ _sso 7 ] '._---_--_ s_,,_ ,<l ,,o,.,cBo,, IC501 1/2 I__'__ Figure 3-1. DVD focus servo, drive...
  • Page 31 The IC506 Servo DSP: CXD8730 on MB-78 board provides the following control the focus servo system. (a) Focus search The optical pickup lens is moved toward a disc to turn on the focus servo. The focus servo loop is turned on when the PI (Pull IN) signal (used for FOK: Focus OK) exceeds the specification (Vc +0.25V) and the FE signal zero-crossing is detected.
  • Page 32 ;topped ,'topped CHI=5_mV: _$/_v CNI_OOmV: 2ms/div 10:1 (2ms_'_v) _2QOk875 ..... ] ..] ..i ..?? ..] ..!..i ..[ ..i_}i '!i ....il_ ......ii ......... ii ....
  • Page 33 The FE signal input to IC506 (DSP CXD8730R) is low frequency boosted and gain-adjusted the internal digital filter, and then output from the DSP as the focus drive signal (F OUT _)P) by the D/A converter inside the DSP. The FOUT signal is input to the focus actuator (coil) drive IC (IC363:BA5981). In IC363, voltage amplification, voltage conversion,...
  • Page 34 The Servo DSP IC provides the following control in the tracking servo system. (a) Tracking gain adjustment The gain of intemal digital filter of IC is automatically adjusted so that the tracking servo loop gain becomes optimum. Consequently, the optimum gain for each disc to be played can be attained, besides correction of gain variations...
  • Page 35 _.t,opped Stopped CHI=500mV 10:1 CHlt506mV: 200us/dfv (Sm$t'div) • i (200_/div) NORM:20_kS/S MORM:.SMS/$ _" 5m:S_/div Figure 3-7. Trv (TE at tracking servo Figure 3-8. TE (enlarged Try) OFF) waveform at DVD waveform at DVD disc, disc, IC506(_)P IC506(_)P Figure 3-9. 1TJ (track jump) waveform at DVD disc, IC506_)P - 40 -...

  • Page 36: Sled Control

    3-2-2. Sled control IC302 LA6527N ,_ledDrive SLOFS SOUT SLDMT _" To sled motor Tracking block SDCNT HYCNT IC506 FromFG-43 board, CXD8730R IC501, IC502 Feedback speed II control by Hall element j Figure 3-10. DVD Sled control (1) Sled control during playing During disc playing, namely, when the focus servo and tracking...
  • Page 37 The sled error signal is passed through the digital filter in IC506 (DSP), and output from the DSP as the SOUT ((_)P) signal from the D/A converter. The SOUT signal is input to DVI ((_P) of the sled drive IC (IC302:LA6527N). The sled drive IC incorporates a speed (motor rotation speed) feed back control using the Hall element.

  • Page 38: Spindle Control

    3-2-3. Spindle Control This section describes the flow of control signals in the spindle servo during DVD playback. The CLV control signal is generated from the RF signal obtained from the optical pickup in ' IC806 (CXD1865) to generate the two servo error signals-disc CLV speed error (MDSO (_ P) and CLV phase error (MDPO (_)P).

  • Page 39: Tilt Control

    3-2-4. Tilt Control TK-47board MB-78 board IC006 SSI33P3720 1(;361 0452 BA5912 2SD2114 CNO06 TIERR cN452 TIMT÷ DRIVER TILT To_ll_m TIMT- TIB_ IC805 1,10_7034 1C804 _8 L..__ TIOFS $H/LGA Offset voffaoe tC806 CDXE730R ,litter Figure. 3-12. Tilt control (1) Tilt servo by tilt sensor Tilt control using the tilt sensor of the optical pickup is performed at the start of DVD playback...
  • Page 40 (2) Tilt offset adjustment minimizing jitter To optimize RF during DVD playback (excluding search), the jitter (JITTER:time:axis fluctuation of the RF signal) is measured, offset is added to the tilt servo loop, and the jitter is minimized. As jitter is adjusted at shipment, normally this adjustment is not required during playback.
  • Page 41 3-3. Servo Operation at CD and Video CD Playing 3-3-1. Optical Pickup Control CD focus servo CH 1154]OmV: lOtrnl/dlv ....i......:......:: ..i......ii ......t......! ..! ......{......! ......: .._..... ,, , •...
  • Page 42 TK-47 board MB-78 board OpticalBlock IC363 IC452 BA5981 IC005 CXA2555Q MC14053 CNO01 CNO05 CN452 C_ FCS* 1 DRIVE To CD focus coil IC503 (BUFF) _cs-j IC506 (DSP) route is the sameas the DVDfocus servo Figure. 3-14. CD focus servo, drive...
  • Page 43 (2) CD tracking servo TK-47 board MB-78 board IC452 IC503 IC506 le_3 MC14053 NJM3403 CXD8730 BA5981 IC005 CXA25550 ToCO_up From tracking c oil optical block Figure 3-15. CD tracking servo CH2=lV 2muild_ (2Wu*/d_] OC I_I ....i ..i ....t ..
  • Page 44 The CDE and CDF signals output from the CD optical pickup are converted to the CD tracking error signal (CDTE (_)P) at IC005 of (CXA2555Q) the TK-47 board. The CDTE signal is input to the switch IC (IC452, MC1405'3) of the MB-78 board. During CD playback, it is passed through...

  • Page 45: Sled Control

    3-3-2. CD Sled Control CD sled control is exactly the same as the DVD. However settings in IC506 (DSP:CXD8730R) differ. 3-3-3. CD Spindle Control As the RF signal is processed inside IC806 (CXD1865), the process from the ARP is the same as the DVD.

  • Page 46: Motor Driver

    Disc loading, unloading, and chucking operations are performed with one DC motor. Its block diagram is dhown in Figure 3-19. 3-4-1. Motor Driver The system controller IC (IC805) controls the open and close of the tray. It monitors sensors of the mechanism conti:ols the operations of the tray motor via the L G/A IC (IC804).

  • Page 47: Differentiation Of Disk Type

    3-5. Differentiation of Disc Type This series can determine three types of discs (CD/DVD-SL/DVD-DL) at one time when performing focus-search. 3-5-1. CD/DVD Differentiation The pit shape and track pitch are quite different between CD and DVD. Because of this difference, TE is not generated even if a large laser spot for CD is shot at a high density disk such as DVD.
  • Page 48 3-6. Block diagram (Servo) TK-47 MR-78 Servo Block ,_ :k;AL _LOCK ITS06 uv_) Rh icoo6 MUt,O DVD PDIC _F HOLO 4Z CXDI86!,R MDpo 2zM DSP ..DVDP_ IA1. 2 ssi33P372oA OVDFE DVO FE <27OOMHz) ..PISW <s.i • TIERR TZ¢ DFCT OVULO ssso...

  • Page 49: Ic Pin Description

    IC PIN DESCRIPTION 4-1. CXD1865R (IC806 oil MB-78 board) 4-1-1. Block Diagram 13T-139, 141-143, 145-147, 149:MAO-MA9 113:WFCK 150:XMWR 114:SC0 R 151:XCAS 116:EXCK 153:XRAS 50:DEC1 117:SBSO 154:XOE 51:NORF 119:SOS0 156-159, 161-164, 52:JITPWM 55:FWON 120:SOCK 166-169, 171-174:MDOO-MD15 90:SDCK 91:XSHD Out,,ut "-- IO:RI:-IN1 92:XSRO 93:XSAK 12:RFIN2...
  • Page 50 4-1-2. Pin Functions Direction Level Pin No. Function Signal Name PLCKI PLCK input PLCKO PLCK output Digital ground RF2 value data input/output Digital positive power supply v_s1 Digital ground ADC reference VRBS ADC reference GNDA1 Analog ground RFIN1 RF input RF input RFIN2 RF input...
  • Page 51 Pin No. Direction Level Function Signal Name Digital ground TESTA Test pin MDSO CLV speed error Digital positive power supply Digital ground MDS 1 CLV speed error Motor on MDP0 CLV phase error MDP1 CLV phase error DFCT Defect detection output NORF NO RF detection...
  • Page 52 Level Function Pin No. Direction Signal Name XWAT Wait Reset XRST Digital positive power supply TEST0 Test pin SCMD Test pin " ETST Test pin Digital ground SD bus clock SDCK XSHD SD bus header XSRQ SD bus REQ XSAK SD bus ACK SDEF SD bus error flag...
  • Page 53 Pin No. Direction Level Function Signal Name Digital ground MNT0 Monitor MNT1 Monitor MNT2 Monitor MNT3 Monitor Digital positive power supply MNT4 Monitor bus MNT5 Monitor bus MNT6 Monitor bus MNT7 Monitor bus ESTB Error information strobe Digital ground DRAM address DRAM address DRAM address Digital positive power supply...
  • Page 54 Pin No. Direction Level Function Signal Name MD09 DRAM data MD10 DRAM data MDll DRAM data Digital ground MD12 DRAM data MD13 DRAM data MD14 DRAM data M-D15 DRAM data PLDIR PLCK direction control Digital ground *Function of direction I [input], O [output], OD [output (open drain)], O(B) [output (bi-direction during test)], B[input/output...

  • Page 55: Block Diagram (Servo)

    4-2. AV Decoder L64020 (MB-78 Board IC203) 4-2-1. Block Diagram < - 62 -...

  • Page 56: Pin Assignment

    4-2-2. Pin Assignment Pin No. Pin No. Pin No.. Signal Name Signal Name Signal Name SBD_7 SBD_6 PD_5 PD_6 SBD_5 SBD_4 PD_7 SBD_3 BLANK SBD_2 CREF SBD1 EXT_OSD_0 SBD_0 EXT_OSD_I EXT_OSD_2 CH_DATA_0 EXT_OSD_3 CH_DATA_I CH_DATA_2 CH_DATA_3 ACLK_441 SYSCLK CH_DATA,_4 ACLK_48 CH_DATA_5 RESET_N ACLK_32...
  • Page 57 Pin No. Signal Name SBD14 SBD_13 SBD_12 SBD_11 SBD_10 SBD_9 SBD_8 SCLK SBA_9 SBA_8 SBA_7 SBA_6 SBA_5 SBA_4 SBA_3 SBA_2 SBA_I SBA_0 SBA_10 SBA_ll SCSI_N SCS_N SRAS_N SRAS_N SWEN SDQM PLLVDD PLLVSS - 64 -...

  • Page 58: Digital Signal Processor Cxd8730R

    4-3. Digital Signal Processor CXD8730R (MB-78 Board IC506) 4:3-1. Pin Assignment PWMO G1012 2 (_ PWM1 G1011 PWM2 GI010 "l HCWHLBS GI09 71 -1 HFS/HMR GI08 70 "1 HR/HRD DGND HX/HINT G}07 SER/PAR GI06 DVCO GIOS/TMC1 [" F lo ' GIO4/TMCO X2/CLKIN ' GlO3,q NT5 DGND...
  • Page 59 4-3-2. Pin Functions This section describes signals. The input/output states of signals are differentiated by the input (I), output (O), and high impedance (Z). Each signal is grouped by function. Type Function Pin ]Signal Name I,I/0 Analog signal pin VRTS Analog AD upper limit reference voltage output.
  • Page 60 Function Signal Name Type HFS/HWR Frame sync signal/host data write strobe signal input for data transmission. In the serial mode, the data transmission frame sync signal is input. In the parallel mode, the data write strobe signal is input. CMOS HX/HINT Host serial data/host interrupt...
  • Page 61 Ivol I Signa, Function Type Name FG/PG counter FGREF FG counter reference pulse signal input. The polarity (Hysteresis) of the input can also be checked by the host output register (bit 10). FGIN FG pulse signal input. The polarity of the input can (Hysteresis) also be checked by the host output register (bit 9).
  • Page 62 Function Type Signal Name AVcc +5V supply pin for analog circuit. 27, 30, 39, 48, AGND Ground for analog circuit. 32, 35, 40, 47, - 69 -...
  • Page 63 4-4. AC3 Decoder MB86342 (MB-78 Board IC104) 4-4-1. Block Diagram B-bus /_-OLIS _'.DUS MCLK1 MCLK2 XRST SGKO EXTIN •- KFSlO CLKGM PSTOP MCORE FS1,FS2 SYNC EXLOCK LRCKI1 LRCKI2 BCKI1 BCKI2 ADIF SDII,SDI2 LRCKO B_KO SDOO-SD03 HCLK -HDIN HDOUT HISF "HCS ..

  • Page 64: Pin Functions

    4-4-2. Pin Functions Function Pin No. Signal Name MCLKI Clock input pin MCLK2 Clock input/output XRST Reset signal input SCKO System clock output pin Master/slave selection L:Master (Crystal oscillation) H:Slave (External clock) S_NC Sync/async selection pin (L:Sync, H:Async) EXTIN System clock (384 fs) input pin 13, 14 FS1, FS2 Sampling...

  • Page 65: Block Diagram

    4-5. Large Gate Array CXD8728 (MB-78 Board IC804) 4-5-1. Block Diagram .£ .£ > > > > "5 .--- 3 o ,---- --=_w = x---_ ..,rr_.N > "_ x_ _, O0 t_ u: ,..%t-_ 0...:-'- ,.._ _" ¢_X _- _.= _ t_-- ""._= _-_×...

  • Page 66: Pin Functions

    4-5-2. Pin Functions Pin No. Function " RD/WR,SHIF Signal Name DVDLDONn I/O, RD/WR DVD laser light/off signal:ON when "L" CDLDONn I/O, RD/WR CD laser light/off signal:ON when "L" CDfDVD I/O, RD/WR Signal differentiating between CD and DVD:DVD when "H". OPN/CLS I/O, RD/WR Tray open/close.
  • Page 67 Pin No. Function Signal Name RD/WR,SHIF TSENS I/O, RD Changer roulette position detection sensor. No groove when "L". Groove is present when "H". DSENS I/O, RD Changer disc presence detection sensor. Present when "H" and absent when "L". I/O, RD DISC detection position (rotary sensor) 0 to 7 value I/O, RD DISC detection position (rotary sensor) 0 to 7 value...
  • Page 68 Function Pin No. RD/WR,SHIF Signal Name SIG1 SHIE OUT SIG2 SHIE OUT XmQ7 SHIF, OUT XCS6n SHIE IN XRDn SHIE IN XLWRn SHIE IN HA21 SHIE IN HA20 SHIE IN SDSPWRn Servo DSP chip select & write Peripheral I/F, OUT CPU clock CPCK SHIE IN...
  • Page 69 Function Pin No. Signal Name RD/WR,SHIF H/W, IN (DIAGN) (CTS) H/W, OUT H/W, IN/OUT SH serial channel I SCLK (GROUP2) or IRQ5 SCKG2, (IRQ5) output AVCK H/W, o'UT AV Enc CXD1914 serial clock CK27M " 'H/W, IN AV CK Resync 27Mclock GAIN6n I/O, RD/WR AUDIO...
  • Page 70 Function Pin No. Signal Name RD/WR,SHIF CLAPBSY I/O, RD When the clap IC MSM6654 is generating sounds, outputs the "H" level. When the power is turned OTASUKE I/O, RD Active "L" level when the help IC NJM2072M needed. DVD/VTR I/O, RD/WR Video control.

  • Page 71: Middle Gate Array Cxd8746 (Ic101 On Mb-78 Board)

    4-6. Middle Gate Array CXD8746 (IC101 on MB-78 board) 4-6-1. Block Diagram < < < t..o _ Joloele£ e_.eO olanv i..-- 83ZVO u:,_: >- I "q 8u.l.Va I _-_ __..1 i 1_ O":L,, 6,ou', S WlIIU61S V P'_m I €_lUU6!_ lO,qUOO r! ' :'Tii •...

  • Page 72: Pin Functions

    4-6-2. Pin Functions Level From/For Function Pin No. Signal Name ARSTI XLOCKI AC3 serial communication SCK21 AC3 serial communication SO21 AC3 serial communication ACSI BSTI 768fs FS768 27M clock MCK27 Test tone on/off DC3D 2ch DAC data switching 2Ch DAC DATA2 Audio signal to 2ch DAC 2Ch DAC...
  • Page 73 From/For Function Level Pin No. Signal Name DATA5 3.3V AC-3 Audio signal (Karaoke) to AC_3 3.3V BCK5 AC-3 Audio signal (Karaoke) to AC_3 LRCK5 3.3V AC-3 Audio signal (Karaoke) to AC_3 FS384 3,3V AC-3 AC3 384fs LRCK3 Karaoke Audio signal to karaoke Karaoke BCK3 Audio signal to karaoke...

  • Page 74: Small Gate Array Cxd8747 (Ic807 On Mb-78 Board)

    4-7. Small Gate Array CXD8747 (MB-78 Board IC807) 4-7-1. Block Diagram SCKO LSB->MSB SCKI Inversion Circuit CK(27MHz) i, XRST HA 0 -8 IAO - 8 HDo-7 IDo-7 i,,. - 81 -...

  • Page 75: Pin Assignment

    4-7-2. Pin Assignment Pin No. BUFF.TYPE Pin No. Signal Name Signal Name BUFF.TYPE TLCHT TLCHT TLCHT TLCHT TLCHT SCKO TLCHT TLCHT XRST SCHMITT BD8T SCHMITT BD8T BD8T TLCHT BD8T TLCHT BD8T BD8T BD8T BDST TLCHT SCKI SCHMITT TLCHT TLCHT TLCHT BD8T BD8T BD8T...

  • Page 76: Overall Block Diagram

    OVERALL BLOCK DIAGRAM 5-1. RF, Serve, Audio, Power Block Diagram DVPS115 '10"; uVP M30 MJt' ... £ f ............. I 1._b.I CN203 D-FFS FL-90BOARD (BVDM30/M35) EL-{}' I}OARD CN1Olr. pLCN4Ol OAOAOAFA -" vz_._: , Dvo w _. cDJ l_ I L %,_-_ CN2O5 I MB-78 BOARD OAO-BC_.OAC-LRO_...

  • Page 77: Signal Processing Block Diagram

    5-2. Signal Processing Block Diagram 'blJl Im2Dli L 'C2D2 ;MHz ,®=-2OOAOD :, __ DVP 50UOD_bD0/U/_00DU ---- 16MX2 SDRAM ION542 CN603 I0 1K-47 BOARD DVD RF CN005 • _DEN i_, ,r-, [COMPONENT_I CDRF ] u_LE_2J _,CDTE, TEATT B-V,"GB ,'_ TIE,TIERR, TIOFS , YS-._OARO I DVDPI, DVDFE AV DEC...
  • Page 78 SONY,...

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