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Philips CEM3000B Service Manual
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Philips CEM3000B Service Manual

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CEM3000B
TROUBLE SHOOTING.................................................................21-22
2011-11-17

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  • Page 1 CEM3000B TROUBLE SHOOTING..............21-22 2011-11-17...
  • Page 2 Press EJ button and take out panel take out A screw in top cover of the unit;Use tweezer to prize up top cover as the blue arrow direction which showed as below picture Use electrical screw bit to take out B,C two screws in left and right side of metal bracket; Then take out D,E screws in panel base 3 Uplift the CD deck mechanism and take out FFC then take out deck mechanism...
  • Page 5 AUX R 4702 R109 R128 CDP_RST RA/DAB+ R110 R208 POWER_IN2 AUX L R129 MP3_CLK RDS ON/OFF DIS AM R189 220K DIS AUX(CEM3000B) 220K C118 R130 MP3_DI EN TA ON(CEM3000) R204 9015S R124 5V_POW_IN1 R131 MP3_DO EN SUB-W 220K DIMMER 1R 1W...
  • Page 6 CIRCUIT DIAGAM SERVO BOARD...
  • Page 7 R955 Q903 Q901 Q902 R956 SC6579 R957 USB_UP USB_DN USB_5V SYS_5V BT_LED LAMP_VCC DATA 2COLOR R913 REMOTE ENCODER ipod SUB/DBB TRACK-UP TRACK-DN KEY2 KEY1 AUX_R AUX_L DISP MENU AUDIO BAND VOL+ VOL- POWER/MUTE 1 0F 1...
  • Page 8 CIRCUIT DIAGAM REMOTE BOARD...
  • Page 9 100nF 100nF DACOUT_R DACOUT_L 100nF VDIG GND-RF GND-RF 100nF 4.7nF VCC-DAC 9018 TCAGCFM GND-1V2 FMMIXDEC VDD-1V2 10nF FMMIXIN RSTN RSTN GND-RF GND-RF RDSINT RDSINT GND-RF 100nF FMPINDRV VDD-1V2 VCC-RF 2.2uF SDA_MOSI TCAM 9018 10nF TOKO TQFP44 pins 10x10 I.C. and SMD socket 100nF PINDDEC VDD-3V3...
  • Page 12 SERVO PCB COMPONENT LAYOUT TOP SIDE VIEW...
  • Page 13 SERVO PCB COMPONENT LAYOUT BOTTOM SIDE VIEW...
  • Page 14 PANEL PCB COMPONENT LAYOUT BOTTOM SIDE VIEW...
  • Page 15 PANEL PCB COMPONENT LAYOUT TOP SIDE VIEW...
  • Page 16 REMOTEL PCB COMPONENT LAYOUT BOTTOM SIDE VIEW...
  • Page 17 REMOTEL PCB COMPONENT LAYOUT TOP SIDE VIEW...
  • Page 18 TUNER PCB COMPONENT LAYOUT BOTTOM SIDE VIEW...
  • Page 20 SET EXPLODER VIEW DRAWING...
  • Page 21 Product Model CEM3000B Tate 2011-11-16 failure failure cause remark phenomena a. To check whether it is connect well of the ISO connector (4 PIN power input ). Whether it is loose of the 15A fuse of the ISO connector, or insert non in place.
  • Page 22 failure failure cause remark phenomena a. To check the antenna of the DAB tuner. b. To check whether the strength of then input signal of the tuner is too weak. c. To check the supply voltage of the 1 pin of TUN1 DAB-TUN should be +1V2 the 2 pin should be +3V3.
  • Page 23 TENTATIVE Version No.18052009 LV47002P Development Specification Proposal (BTL 4 channel Car Audio Power Amplifier) The LV47002P is the IC for 4-channel BTL power amplifier that is developed for car audio system. Pch DMOS in the upper side of the output stage and Nch DMOS in the lower side of the output stage are complimentary.
  • Page 24 TENTATIVE 4. Maximum Ratings at Ta = 25℃ ℃ ℃ ℃ Parameter Symbol Conditions Ratings Unit Maximum supply Voltage Vcc max 1 No signal, t=1 minute Vcc max 2 During operations Maximum output current Io peak Per channel 4.5/ch Allowable Power dissipation Pd max With an infinity heat sink ℃...
  • Page 25 TENTATIVE 7. LV47002P Test and Application circuit rotective circ it i le ilter circ it Lo Level rotective circ it itch The components and constant values within the test circuit are used for confirmation of characteristics and are not guarantees that incorrect or trouble will not occur in application equipment. Note : Information in this document is subject to change without notice.
  • Page 26 TENTATIVE 8. Explanation for the functions 1. Standby switch function (pin 4) Threshold voltage of the pin 4 is set by about 2VBE. The amplifier is turned on by the applied voltage of 2.5V or more. Also, the amplifier is turned off by the applied voltage of 0.5V or less.
  • Page 27 TENTATIVE 4. Self-diagnosis function (pin 25) By detecting the unusual state of the IC, the signal is output to the pin 25. Also, by controlling the standby switch after the signal of the pin 25 is detected by the microcomputer, the burnout of the speaker can be prevented.
  • Page 28 TENTATIVE Icco - Vcc - Vcc RL=Open RL=Open R =0Ω R =0Ω Vcc (V) Vcc (V) Po - Vcc(THD=10%) Po - f(THD=1%) f=1kHz RL=4Ω THD=10% all channel is similar all channel is similar Vcc=14.4V RL=4Ω THD=1% 1000 10000 100000 Vcc (V) f (Hz) THD - Po(f=1kHz) THD - Po(f=100Hz)
  • Page 29 TENTATIVE f-Response - Rg Vcc=14.4V RL=4Ω all channel is similar Vcc=14.4V RL=4Ω Vo=0dBm 1000 10000 100000 1000 10000 100000 f (Hz) Rg ( CH.Sep - f(CH1→ → → → ) CH.Sep - f(CH2→ → → → ) ch2→ch1 Vcc=14.4V ch1→ch2 Vcc=14.4V RL=4Ω...
  • Page 30 TENTATIVE Offset DIAG - Vcc Pd - Po RL=4Ω f=1kHz R =0Ω RL=4Ω Pd=Vcc×Icc-Po×4ch Detection Level Vcc=14.4V Vcc=16V Vcc (V) Po (W) Mute ATT - V Mute Icco - Vst Vcc=14.4V RL=Open R =0Ω Vcc=14.4V RL=4Ω Vo=20dBm V Mute(V) Vst (V) Note : Information in this document is subject to change without notice.

  • Page 32: Product Family

    FEDD56V16160F-02 1 Semiconductor This version: March. 2001 Previous version : January. 2001 MSM56V16160F 2-Bank × × × × 524,288-Word × × × × 16-Bit SYNCHRONOUS DYNAMIC RAM DESCRIPTION The MSM56V16160F is a 2-Bank × 524,288-word × 16-bit Synchronous dynamic RAM fabricated in Oki’s silicon-gate CMOS technology.

  • Page 33: Pin Configuration (Top View)

    FEDD56V16160F-02 1 Semiconductor MSM56V16160F PIN CONFIGURATION (TOP VIEW) DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 LDQM UDQM 50-Pin Plastic TSOP (II) (K Type) Pin Name Function Pin Name Function System Clock UDQM, LDQM Data Input / Output Mask Chip Select Data Input / Output Clock Enable Power Supply (3.3V)

  • Page 34: Pin Description

    FEDD56V16160F-02 1 Semiconductor MSM56V16160F PIN DESCRIPTION Fetches all inputs at the “H” edge. Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE, UDQM and LDQM. Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated.

  • Page 35: Block Diagram

    FEDD56V16160F-02 1 Semiconductor MSM56V16160F BLOCK DIAGRAM Latency Progra- & Burst Controller ming Controller Register Timing Register UDQM Bank LDQM Controlle Internal Col. Address Counter Input Input A0−A11 Data Buffers Registe Column Column Address Decoders Buffers Sense −DQ16 Amplifiers Read Output Data Buffers Internal...

  • Page 36: Recommended Operatiing Conditions

    FEDD56V16160F-02 1 Semiconductor MSM56V16160F ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on Any Pin Relative to V –0.5 to V + 0.5 Supply Voltage –0.5 to 4.6 Storage Temperature –55 to 150 °C Power Dissipation Short Circuit Output Current -20 to 85 °C Operating Temperature...
  • Page 37 FEDD56V16160F-02 1 Semiconductor MSM56V16160F DC CHARACTERISTICS MSM56V16160 Condition Parameter F-10 Unit Note Symbol Bank Others Min. Max. Min. Max. Output High     =−2.0mA Voltage Output Low     =2.0mA Voltage Input Leakage    −10 −10 µA...

  • Page 38: Power-On Sequence

    FEDD56V16160F-02 1 Semiconductor MSM56V16160F Mode Set Address Keys CAS Latency Burst Type Burst Length BT = 0 BT = 1 Reserved Sequential Interleave Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved Notes: A7, A8, A9, A10 and A11 should stay “L” during mode set cycle. MSM56V16160F support two methods of Power on Sequence.
  • Page 39 FEDD56V16160F-02 1 Semiconductor MSM56V16160F AC CHARACTERISTICS (1/2) Note 1,2 MSM56V16160 Parameter Symbol Unit Note F-10 Min. Max. Min. Max.   CL = 3   Clock Cycle Time CL = 2   CL = 1   CL = 3 Access Time from ...
  • Page 40 FEDD56V16160F-02 1 Semiconductor MSM56V16160F AC CHARACTERISTICS (2/2) Note 1,2 MSM56V16160 Parameter Symbol Unit Note F-10 Min. Max. Min. Max. Data Input Mask Time from Write Cycle Command Data Output High Impedance Time Cycle from Precharge Command Active Command Input Time from Mode Register Set Command Input Cycle (Min.)

  • Page 41: Timing Chart

    FEDD56V16160F-02 1 Semiconductor MSM56V16160F TIMING CHART CAS Latency= = = = 2, Burst Length= = = = 4 Read & Write Cycle (Same Bank) @CAS ADDR Qa2 Qa3 Db0 Db1 Db2 Db3 UDQM, LDQM Row Active Row Active Read Command Precharge Command Write Command Precharge Command...
  • Page 42 FEDD56V16160F-02 1 Semiconductor MSM56V16160F CAS Latency= = = = 2, Burst Length=4 Single Bit Read-Write-Read Cycle (Same Page) @CAS High ADDR UDQM, LDQM Row Active Write Command Precharge Command Read Command Read Command 11/31...
  • Page 43 FEDD56V16160F-02 1 Semiconductor MSM56V16160F *Note: 1. When CS is set “High” at a clock transition from “Low” to “High”, all inputs except CKE, UDQM and LDQM are invalid. 2. When issuing an active, read or write command, the bank is selected by A11. Active, read or write Bank A Bank B...
  • Page 44 FEDD56V16160F-02 1 Semiconductor MSM56V16160F CAS Latency= = = = 2, Burst Length=4 Page Read & Write Cycle (Same Bank) @CAS High Bank A Active ADDR Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 ∗Note 2 ∗Note 1 UDQM, LDQM Read Command Write Command Precharge Command Read Command...
  • Page 45 FEDD56V16160F-02 1 Semiconductor MSM56V16160F Read & Write Cycle with Auto Precharge @ Burst Length= = = = 4 High ADDR CAS Latency=1 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 A-Bank Precharge Start UDQM, LDQM CAS Latency=2 Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 A-Bank Precharge Start UDQM,...
  • Page 46 FEDD56V16160F-02 1 Semiconductor MSM56V16160F Bank Interleave Random Row Read Cycle @CAS Latency=2, Burst Length=4 High ADDR QAa0 QAa1 QAa2 QAa3 QBb1 QBb2 QBb3 QBb4 QAc0 QAc1 QAc2 QAc3 UDQM, LDQM Row Active Read Command Read Command Row Active (A-Bank) (B-Bank) (A-Bank) (B-Bank) Read Command...
  • Page 47 FEDD56V16160F-02 1 Semiconductor MSM56V16160F Bank Interleave Random Row Write Cycle @CAS Latency=2, Burst Length=4 High ADDR DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 UDQM, LDQM Row Active Row Active Precharge Command Write Command (A-Bank) (B-Bank) (A-Bank) (A-Bank) Precharge Command Write Command Precharge Command...
  • Page 48 FEDD56V16160F-02 1 Semiconductor MSM56V16160F Bank Interleave Page Read Cycle @CAS Latency=2, Burst Length=4 High ∗Note 1 ADDR QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 UDQM, LDQM Row Active Row Active Read Command Precharge Command (A-Bank) (B-Bank) (B-Bank)
  • Page 49 FEDD56V16160F-02 1 Semiconductor MSM56V16160F CAS Latency=2, Burst Length= = = = 4 Bank Interleave Page Write Cycle @CAS High ADDR DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 UDQM, LDQM Row Active Row Active Write Command (A-Bank) (B-Bank) (B-Bank) Precharge Command...
  • Page 50 FEDD56V16160F-02 1 Semiconductor MSM56V16160F CAS Latency=2, Burst Length=4 Bank Interleave Random Row Read/Write Cycle @CAS High ADDR QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 QAc3 UDQM, LDQM Row Active Row Active Write Command Read Command (A-Bank) (B-Bank) (B-Bank) (A-Bank)
  • Page 51 FEDD56V16160F-02 1 Semiconductor MSM56V16160F CAS Latency=2, Burst Length=4 Bank Interleave Page Read/Write Cycle @CAS High CAa0 CBb0 CAc0 ADDR QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 QAc2 QAc3 UDQM, LDQM Read Command Write Command Read Command (A-Bank) (B-Bank) (A-Bank) 20/31...
  • Page 52 FEDD56V16160F-02 1 Semiconductor MSM56V16160F CAS Latency=2, Burst Length=4 Clock Suspension & DQM Operation Cycle @CAS ∗Note 1 ∗Note 1 ADDR Qa0 Qa1 Qb0 Qb1 ∗Note 3 ∗Note 2 UDQM, LDQM CLOCK Read Command Write Write DQM Read DQM Row Active Suspension Read Command Write...
  • Page 53 FEDD56V16160F-02 1 Semiconductor MSM56V16160F CAS Latency=2, Burst Length=4 Read to Write Cycle (Same Bank) @CAS ∗Note 1 ADDR Db0 Db1 Db2 Db3 UDQM, LDQM Precharge Command Row Active Read Command Write Command *Note: 1. In Case CAS latency is 3, READ can be interrupted by WRITE. The minimum command interval is [burst length + 1] cycles.
  • Page 54 FEDD56V16160F-02 1 Semiconductor MSM56V16160F Read Interruption by Precharge Command @Burst Length= = = = 8 High ADDR CAS Latency=1 ∗Note 1 Qa0 Qa1 Qa3 Qa4 Qa5 UDQM, LDQM CAS Latency=2 ∗Note 1 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 UDQM, LDQM CAS Latency=3 ∗Note 1 Qa0 Qa1 Qa2 Qa3 Qa4...
  • Page 55 FEDD56V16160F-02 1 Semiconductor MSM56V16160F Burst Stop Command @Burst Length=8 High ADDR CAS Latency=1 Qa0 Qa1 Qa2 Qa3 Qa4 Qb0 Qb1 Qb2 Qb3 Qb4 UDQM, LDQM CAS Latency=2 Qa0 Qa1 Qa2 Qa3 Qa4 Qb0 Qb1 Qb2 Qb3 Qb4 UDQM, LDQM CAS Latency=3 Qa0 Qa1 Qa2 Qa3 Qa4 Qb0 Qb1 Qb2 Qb3 Qb4 UDQM,...
  • Page 56 FEDD56V16160F-02 1 Semiconductor MSM56V16160F Power Down Mode @CAS Latency=2, Burst Length=4 ∗Note 2 ∗Note 1 (min.) ADDR Qa0 Qa1 Qa2 UDQM, LDQM Power-down Read Command Entry Active Power-down Clock Clock Precharge Command Exit Suspension Suspension Exit Entry *Note: 1. When both banks are in precharge state, and if CKE is set low, then the MSM56V16160F enters power-down mode and maintains the mode while CKE is low.
  • Page 57 FEDD56V16160F-02 1 Semiconductor MSM56V16160F Self Refresh Cycle ADDR Hi-Z UDQM, LDQM Self Refresh Entry Self Refresh Exit Row Active 26/31...
  • Page 58 FEDD56V16160F-02 1 Semiconductor MSM56V16160F Mode Register Set Cycle Auto Refresh Cycle High High ADDR Hi - Z Hi - Z UDQM, LDQM New Command Auto Refresh Auto Refresh 27/31...
  • Page 59 FEDD56V16160F-02 1 Semiconductor MSM56V16160F FUNCTION TRUTH TABLE (Table 1) (1/2) Current ADDR Action State Idle ILLEGAL 2 ILLEGAL 2 Row Active NOP 4 Auto-Refresh or Self-Refresh 5 OP Code Mode Register Write Row Active CA, A10 Read CA, A10 Write ILLEGAL 2 Precharge ILLEGAL...
  • Page 60 FEDD56V16160F-02 1 Semiconductor MSM56V16160F FUNCTION TRUTH TABLE (Table 2) (2/2) Current ADDR Action State ILLEGAL Write with Auto ILLEGAL 2 RA, A10 Precharge ILLEGAL NOP --> Idle after t RP Precharge NOP --> Idle after t RP ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 NOP 4 ILLEGAL...
  • Page 61 FEDD56V16160F-02 1 Semiconductor MSM56V16160F FUNCTION TRUTH TABLE for CKE (Table 2) Current State (n) CKEn-1 CKEn ADDR Action INVALID Self Refresh Exit Self Refresh --> ABI Exit Self Refresh --> ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Power Down Exit Power Down -->...
  • Page 62 FEDD56V16160F-02 1 Semiconductor MSM56V16160F NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product.
  • Page 63 S5L8035Ui (Preliminary Spec) PRODUCT OVERVIEW S5L8035Ui CDMP3 SOC V1.1...

  • Page 64: Product Overview

    PRODUCT OVERVIEW S5L8035Ui (Preliminary Spec) PRODUCT OVERVIEW INTRODUCTION S5L8035Ui Audio MP3CDP SoC provides a cost-effective solution for Audio CD application. The S5L8035Ui SoC solution presents a rich set of features for a typical stand-alone Audio CD system: high-quality audio processing, fully embedded CD front-end (RF, servo control, and CD-DSP), up to 4megabit flash memory support.
  • Page 65 S5L8035Ui (Preliminary Spec) PRODUCT OVERVIEW ARCHITECTURE • 135MHz CalmADM (CalmRISC16, CalmMAC24, 4KB I-Cache, 12KB D-Cache, two stream buffers) • Front-end controller (CD 4x compatible digital servo) • Audio stream codec (Audio DSP: CalmMAC24) • On-chip clock generator with PLL • Multi Boot System (External S-Flash, Internal ROM, Internal SRAM, External SDRAM(EDO)) •...
  • Page 66 PRODUCT OVERVIEW S5L8035Ui (Preliminary Spec) FEATURES • 8 entries (6-words) with one valid bit and one Processor Architecture dirty bit per a Mac data line • CalmADM3 MCU+DSP solution • 8 entries (4-words) with one valid bit and one • CalmRISC16: 16-bit RISC architecture dirty bit per a Calm data line •...
  • Page 67 S5L8035Ui (Preliminary Spec) PRODUCT OVERVIEW FEATURES (CONTINUED) Memory Controller Timers • Supports 16-bit or 8-bit data bus width for 16M SDRAM interface. (up to 128Mbits) • 16-bit timer 1, 2 – Interval, free run, one shot and capture mode • SDRAM Interface Supports four bank, 8-bit or –...
  • Page 68 S5L8035Ui (Preliminary Spec) PRODUCT OVERVIEW IR Input FEATURES (CONTINUED) • Supports consumer electronic IR protocol. USB1.1 Host Interface • Open HCI Rev1.0 compatible • No Bi-directional or Tri-state Buses Frequency Counter • No level sensitive Latches • Supports FM/AM Frequency Counter •...
  • Page 69 S5L8035Ui (PRELIMINARY SPEC) PRODUCT OVERVIEW Figure 1-2. S5L8035Ui 128 Pin Assignments...

  • Page 70: Electrical Data

    S5L8035Ui (Preliminary Spec) ELECTRICAL DATA ELECTRICAL DATA ABSOLUTE MAXIMUM RATINGS Table 29-1. Absolute Maximum Rating Symbol Parameter Rating Unit V DD 1.2V core DC supply voltage V DDP 3.3V I/O DC supply voltage V IN DC input voltage 3.3 V input buffer V OUT DC output voltage 3.3 V output buffer...

  • Page 71: Electrical Characteristics

    ELETRICALL DATA S5L8035Ui (Preliminary Spec) D.C. ELECTRICAL CHARACTERISTICS Table 29-3. Normal I/O PAD D.C. Electrical Characteristics (V DD = 1.65V~3.60V, T OPR = industrial -40 to 85 ℃) Symbol Condition Unit High Level Input Voltage LVCMOS 0.7VDD VDD+0.3 Interface Low Level Input Voltage LVCMOS -0.3 0.3VDD...

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